Many circuits benefit from reduced power consumption. This is particularly the case for devices which operate on scavenged power, such as thermally-harvested energy (via a Peltier, thermocouple, or similar device), vibration-harvested energy (through a magnet and coil, or piezoelectric transducer, for example), or photoelectric-harvested energy (via a solar cell, for example). Circuits which are powered by a battery with an ultra-low self discharge rate, for example the EnerChip solid state batteries sold by Cymbet, also benefit from reduced power consumption.
Current circuit design techniques and devices are limited in their ability to provide high performance at ultra-low bias currents due to intrinsic device behavior. For example, a low power bandgap described in “An ultra low power bandgap operational at supply as low as 0.75V” by Vadim Ivanov, et al. ESSCIRC 2011 consumes 200 nA, which is a substantial amount of current for scavenged power supplies. In some applications a continuous current is provided from an energy scavenger, and the energy is stored until a certain threshold sufficient for an operation is reached. Once the threshold is reached, the device wakes up, performs an operation, and then goes back to sleep. Reduced current requirements from supervisory-function circuit blocks such as timers, oscillators, power-on-reset circuits, voltage references, or comparators translate directly into more useful energy for performing desired functionality, such as sending or receiving a packet of data over a radio.
As CMOS technology has decreased in geometry the gate oxide thickness has been continuously reduced. For device geometries below about 0.18 um, gate leakage becomes considerable. Gate leakage from these ultra-deep submicron CMOS processes has been identified as an undesired behavior with many undesirable properties. For example, in a microprocessor, gate-oxide leakage contributes to high standby current. Other applications have identified a minimum frequency below which the transistor no longer provides current gain for certain device dimensions and bias points (see, e.g.: “Analog Circuits in Ultra-Deep-Submicron CMOS”, IEEE Journal of Solid State Circuits, Vol. 40, No. 1, January 2005, pp. 132-143).
A need therefore exists for circuits that provide high-performance at reduced power consumption, since smaller-sized scavenging power supplies could be used, since devices could be operated in lower intensity conditions (e.g., dim light for solar collection, smaller temperature differences for thermal harvesters), and since additional or improved functionality may be provided as a result of reduced power consumption (e.g., more frequent temperature measurements).